As is generally well known in CMOS digital integrated circuits normal logic levels are (1) a low or "0" logic state which is represented by a lower power supply potential (V.sub.SS) and (2) a high or "1" logic state which is represented by upper power supply potential (V.sub.CC). The lower power supply potential V.sub.SS is usually connected to an external ground or 0 volt and the upper potential power supply V.sub.CC is typically connected to a voltage source referenced above ground, i.e., +5.0 volts. It is often desirable to limit the voltage swings of CMOS circuits so as to improve the speed of signal transition through the circuits. One method of limiting the voltage swing is controlling the high level voltage (V.sub.OH) on the output of a logic gate. This method reduces the voltage swing window on the output's high-to-low transition to trip the threshold voltage of the following logic gate but keeps the same voltage swing window on the low-to-high transition. As a result, the operation of the high-to-low transition is faster than if the V.sub.OH is not controlled. Although this method is applicable to all the logic gates in an integrated circuit, it is particularly useful in output buffers driving high capacitive loads and interfacing with other integrated circuits because it reduces ground noise on the VSS power supply bus, as explain later. Ground noise is a major problem encountered in designing high speed output buffers since it causes false data sensing and degradation of the output logic levels.
While clamp circuits in CMOS technology are available to perform the function of limiting the V.sub.OH voltage, known clamp circuits suffer from the disadvantage of consuming too much power or degrading the speed performance of the output low-to-high transition.
Hence, there is a long felt but unsatisfied need for an improved clamp circuit for lowering the ground noise at the output of a device while not having the power consumption of prior art clamping circuits. In addition, the circuit should also be one which can function at improved operating speeds of known clamp circuits and should be easy to implement in existing circuitry. The present invention addresses such a need.
An example of this type of circuit is shown in FIG. 2. FIG. 2 comprises the a schematic of a prior art clamping circuit 200. As explained earlier, while clamp circuits are available to limit V.sub.OH voltage, prior art clamp circuits suffer from the disadvantage of consuming too much power or degrading the speed performance of the output low-to-high transition.